The present disclosure generally relates to a semiconductor structure, and particularly to a semiconductor structure having dual isolation structures and a doped semiconductor back gate region self-aligned to at least one overlying active area, and methods of manufacturing the same.
Back gate biasing is a useful method for adaptive power management. Planar fully depleted semiconductor-on-insulator (SOI) devices with a thin buried oxide layer (BOX) can be employed to introduce a back gate bias voltage that can independently control device performance without requiring changes to settings at other device nodes. For back gate biasing to be area-efficient, i.e., to provide a back gate biasing scheme that does not require an excessive device area, a group of transistors having the same polarity and target threshold voltage should share a single back gate electrode. However, each back gate electrode should be electrically isolated from adjacent transistors or any back gate electrodes thereof, which require different bias voltages.
Conventional schemes that employ back gate electrodes do not provide self-alignment between a back gate electrode and active areas thereabove because the back gate electrode is patterned separately from the active areas. Other schemes contemplate formation of shallow trenches to an excessive depth that is not practical to implement for advanced semiconductor devices having small dimensions. A back gate device having an area-efficient design and an integration scheme to manufacture such a back gate device are thus desired.